Gain advanced knowledge of System Verilog language for the verification of digital integrated circuits, and get introduced to the Universal Verification Methodology.

The course extends the knowledge of the System Verilog (SV) language for the verification of digital integrated circuits
and introduces the Universal Verification Methodology (UVM). Advanced SV mechanisms, such as assertions, transactions
and inter-process communications are covered as a necessary preparation and introduction to UVM. Common UVM
hierarchy with associated mechanisms for instantiation, connection, communication and simulation execution phases are
covered. Finally, an example of a typical comprehensive UVM project is covered in detail during the course.

Course topics:

System Verilog (SV) inter-process communication; SV events, mailboxes, semaphores;
SV Assertions; Immediate assertions, Concurrent assertions;
SV Transactions; The importance of transactions and their role in SV;
Universal Verification Methodology (UVM) introduction with hierarchy analysis;
Verification in SV and its evolution towards UVM;
The importance of the UVM templates – predefined hierarchy;
UVM execution phases;
UVM communication paths;
UVM communication between building blocks, Analysis Ports and TLM ports
UVM messaging; UVM mechanism form message generation and its importance;
UVM top view on relations between blocks; Configuration database uvm_config_db and its importance; Factory concept;
Final UVM example; Block by block example.