System Verilog for Digital IC Verification

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System Verilog for Digital IC Verification


Understand System Verilog for digital integrated circuit verification, covering basic language constructs.


Gain a fundamental understanding of SV language features such as data types, operators, simulation time concepts, different types of assignments, etc. Final topics include OOP concepts, randomization, and coverage.

Course topics:

  • SV types, operators, literals
  • SV procedural and continuous assignments, blocking and nonblocking assignments
  • Simulation time concept and simulation steps
  • SV modules, programs, interfaces, and connections among them
  • SV tasks and functions
  • Race condition
  • SV Scheduler
  • SV Clocking blocks
  • OOP concepts in SV
  • Parent and child classes, inheritance, virtual methods, polymorphism
  • Directed vs. random testing
  • Randomization of data and randomization of commands
  • Constrained randomization
  • Code coverage, data-oriented coverage, control-oriented coverage
  • Coverage hierarchy, cover groups, cover points, bins


Software: Students should create a free private account on EDA Playground: Edit Code

Hardware: Computer with an Internet connection, working speakers, and microphone.

Prior knowledge: Participants should have basic knowledge of digital design with an introductory level of HDL languages like VHDL or Verilog.