Prof. Dr. Nebojša Pjevalica

Prof. Dr. Nebojša Pjevalica

Prof. Dr. Nebojsa Pjevalica is a Full Professor at the University of Novi Sad, teaching digital design and verification courses. He has authored or co-authored more than 50 scientific papers. His research interests are in the areas of IC verification, digital and HW design. In 2022 he published the first textbook in the Serbian language on digital IC verification, based on System Verilog and UVM.

His industrial experience covers the field of digital verification, digital design, and system-level architecture. As a contractor, he worked for companies like Bosch Sensortec Germany, Cirrus Logic USA, Apex Microtechnology USA, TTTech Austria, RT-RK Serbia, and many others.

References

  • Pjevalica, V. Pjevalica and N. Petrovic, "The Consumer and the Power Grid: Evolution of Problems and Solutions," in IEEE Consumer Electronics Magazine, doi: 10.1109/MCE.2021.3076752.
  • Pjevalica, V. Pjevalica and N. Petrovic, “Advances in concurrent computing for digital stochastic measurement simulation,” in Journal of Circuits Systems and Computers, doi: 10.1142/s0218126620500334
  • Pjevalica, N. Pjevalica and N. Petrović, "Cloud Based Data Acquisition via IoT for Electric Power Quality Monitoring," Zooming Innovation in Consumer Technologies Conference (ZINC), Novi Sad, Serbia, doi: 10.1109/ZINC.2019.8769386.

Courses

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System Verilog for Digital IC Verification

5
(2)

Understand System Verilog for digital integrated circuit verification, covering basic language constructs.

Gain a fundamental understanding of SV language features such as data types, operators, simulation time concepts, different types of assignments, etc. Final topics include OOP concepts, randomization, and coverage.

Course topics:

  • SV types, operators, literals
  • SV procedural and continuous assignments, blocking and nonblocking assignments
  • Simulation time concept and simulation steps
  • SV modules, programs, interfaces, and connections among them
  • SV tasks and functions
  • Race condition
  • SV Scheduler
  • SV Clocking blocks
  • OOP concepts in SV
  • Parent and child classes, inheritance, virtual methods, polymorphism
  • Directed vs. random testing
  • Randomization of data and randomization of commands
  • Constrained randomization
  • Code coverage, data-oriented coverage, control-oriented coverage
  • Coverage hierarchy, cover groups, cover points, bins

Requirements

Software: Students should create a free private account on EDA Playground: Edit Code
Hardware: Computer with an Internet connection, working speakers, and microphone.
Prior knowledge: Participants should have basic knowledge of digital design with an introductory level of HDL languages like VHDL or Verilog.